Advances in EDA design methodologies led

FPGAs have become some of the most important drivers for development of leading edge semiconductor technology. The complexity of programmable devices, and their integration of diverse high-performance functions, provides excellent vehicles for testing new processes. It’s no accident that Intel has selected Achronix and Tabula, both makers of programmable devices, as the only partners that have been granted access to their 22 nm 3D Tri-Gate (FinFET) process. In February, Intel also announced an agreement with Altera, which will enable the company to manufacture FPGAs using their next-generation 14 nm Tri-Gate process.

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In parallel with driving manufacturing, FPGA technology development must also include enhancements to design tools and flows. As vendors strive to make their devices more SoC- and ASIC-like, they are also adopting standards and collaborating with EDA companies to integrate their tools more seamlessly. These collaborations are producing great benefits for designers, as FPGA design methodologies are leading the way in areas that the EDA industry has long been promising new capabilities, such as in Electronic System Level (ESL) synthesis, IP integration and re-use, and higher-level tools for software/hardware co-design.

FPGA design methodologies have long integrated EDA point tools, such as simulation and PCB design, into FPGA vendor’s design platforms. Now, vendors such as Synopsys, with their Synplicity tools, and Xilinx with Vivado, are collaborating to build more complete integrated top-to-bottom flows. To address the greater complexity of FPGAs that may now contain up to two million equivalent logic cells, Synopsys has added Hierarchical Project Management (HPM) to Synplicity. HPM supports distributed design teams and parallel development, enabling partitioning of RTL and sharing of design debug tasks. Xilinx has adopted the industry-standard Synopsys Design Constraint (SDC) timing constraints (to replace Xilinx proprietary UDC) in a design flow that can be driven from standard Verilog HDL.








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